--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   10:27:37 11/30/2010
-- Design Name:   
-- Module Name:   E:/Dev/VHDL/copro/tb_start_monitoring.vhd
-- Project Name:  copro
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: CORE_LEFT
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.constants.all;


ENTITY tb_start_monitoring IS
END tb_start_monitoring;
 
ARCHITECTURE behavior OF tb_start_monitoring IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
	component CORE_LEFT
	port (
		-- Systesm signals
		clk			: in std_logic;
		reset		: in std_logic;
		
		-- Input from coming from the processor
		data_in		:	in std_logic_vector(DATA_SIZE-1 downto 0);
		addr		:	in std_logic_vector(ADDR_SIZE-1 downto 0);
		rd_en		:	in std_logic;
		wr_en		:	in std_logic;
		
		-- Output signals going to the processor
		data_out	:	out std_logic_vector(DATA_SIZE-1 downto 0);
		req_irq		:	out std_logic;
		
		-- Output signals going to the monitoring chain : Core_Right
		shift		:	out std_logic;
		capture		:	out std_logic;
		update		:	out std_logic;
		gwen		:	out std_logic;
		gw_reset		:	out std_logic;
		hw_and_sw_reset : out std_logic;
		tdi			:	out std_logic;
		-- Input signal coming from the monitoring chain
		tdo			:	in std_logic
		);
end component;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '1';
   signal data_in : std_logic_vector(31 downto 0) := (others => '0');
   signal addr : std_logic_vector(12 downto 0) := (others => '0');
   signal rd_en : std_logic := '0';
   signal wr_en : std_logic := '0';
   signal tdo : std_logic := '1';

 	--Outputs
   signal data_out : std_logic_vector(31 downto 0);
   signal req_irq : std_logic;
   signal shift : std_logic;
   signal capture : std_logic;
   signal update : std_logic;
   signal gwen : std_logic;
   signal gw_reset : std_logic;
   signal hw_and_sw_reset : std_logic;
   signal tdi : std_logic;

   -- Clock period definitions
   constant clk_period : time := 1ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: CORE_LEFT PORT MAP (
          clk => clk,
          reset => reset,
          data_in => data_in,
          addr => addr,
          rd_en => rd_en,
          wr_en => wr_en,
          data_out => data_out,
          req_irq => req_irq,
          shift => shift,
          capture => capture,
          update => update,
          gwen => gwen,
		  gw_reset => gw_reset,
		  hw_and_sw_reset => hw_and_sw_reset,
          tdi => tdi,
          tdo => tdo
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
	tdo_stim : process
	begin
		tdo <= '1';
		wait for clk_period*3;
		tdo <= '0';
		wait for clk_period*2;
	end process;

   -- Stimulus process
   stim_proc: process
   begin		
      wait for clk_period*1.5;	
	reset <= '0';
      wait for clk_period;
	  
	  -- reset address
	  rd_en <= '0';
	  wr_en <= '0';
	  addr <= (others => '0');
	  wait for clk_period;

      
	  -- set scan period
	  wr_en <= '1';
      data_in <= X"0000000F";
	  addr(SCAN_PERIOD_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;


	  -- Set Monitoring Length
	  wr_en <= '1';
      data_in <= X"00000035";
	  addr(MON_LEN_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;

	  -- set scan period
	  wr_en <= '1';
      data_in <= X"0000000B";
	  addr(SCAN_PERIOD_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
	  -- set Configuration String
	  wr_en <= '1';
      data_in <= X"00000005";
	  addr(CONFIG_BUFFER_BASE_ADDR) <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
	  -- start monitoring	  
      data_in <= CMD_START;
	  addr(CMD_ADDR) <= '1';
	  wr_en <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  wait for clk_period;
	  
      data_in <= CMD_NOP;
	  addr(CMD_ADDR) <= '1';
	  wr_en <= '1';
	  wait for clk_period;
	  addr <= (others => '0');
	  wr_en <= '0';
	  
	  
      wait;
   end process;

END;
